The present invention relates generally to the fabrication of semiconductor circuits, and more particularly to the fabrication of very large-scale integrated (VLSI) circuits.
Recent developments in processes for fabricating MOS VLSI integrated circuits have resulted in MOS devices that are capable of operating at higher speeds with smaller geometries. As the devices continue to shrink in size, it becomes increasingly difficult to achieve the desired low junction capacitance, acceptable device punchthrough voltages, and acceptable junction avalanche breakdowns in devices fabricated by the current bulk silicon MOSFET processes. Part of the reason for this lies in the present practice of using blanket threshold and/or channel stop implants which are simultaneously implanted beneath the MOSFET channel regions and at or immediately beneath the metallurgical junctions of the MOSFET source-drain regions. While this practice provides generally adequate results at device channel lengths of one micron or greater, smaller devices having submicron channel lengths exhibit high junction floor capacitance and lower diode avalanche breakdowns, as well as reduced transistor punchthrough characteristics.
There is thus a need for an improved method of fabricating submicron VLSI circuits in which these last-mentioned effects are minimized. This is achieved in the present invention by self-aligning the threshold and punchthrough implants underneath the gate electrode, such that the MOSFET's gate electrode and the diffused, high-dose source and drain regions do not receive these implants.